CD Skripsi

Desain Filter Pasif Untuk Mereduksi Rugi-Rugi Harmonisa Akibat Variasi Beban Pada Laboratorium Komputer Dan Jaringan Teknik Elektro Universitas Riau

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This study presents a harmonic filter design to reduce losses due to variations in the load harmonics on Computers and Networks Laboratory of Electrical Engineering, University of Riau. Filter design is using ETAP software 7.5. Design passive filter using parameters from measurements made on the electrical panel Laboratory of Computer and Network by using a measuring instrument power quality analyzer KEW 6310. The parameters used are the active power (watts), reactive power (Var), apparent power (VA), and power factor (cos φ). ETAP simulation analysis process is done by modeling the entire charging circuit parameters with the actual conditions approach such as power grids, transformers, and cables. Harmonic orders reduced are order 5, order 7 and order 11. Harmonic filter is designed for all tests in order to meet the current THD is allowed IEEE standard 519-1992 by 5%. Eight harmonic filters has been done in this case which three filters for harmonic 5th, three filters for harmonic 7th, and two filters for harmonic order 11th.
Keywords: Passive Filter, Harmonic Order, ETAP

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Ketersediaan

Informasi Detail

Judul Seri

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No. Panggil

07 04. 114 (0011)

Penerbit

Pekanbaru : Universitas Riau - Fakultas Teknik - Teknik Elektro S 1., 2014

Deskripsi Fisik

xvii, 79 hlm.: ill.; 29 cm

Bahasa

ISBN/ISSN

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Klasifikasi

07 04. 114 (0011)

Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

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Subjek

ELEKTRO

Info Detail Spesifik

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Pernyataan Tanggungjawab

DAUS

Versi lain/terkait

Lampiran Berkas

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